Research and Development of the Delay Compensation Mechanism for Global Clock Propagation Through FPGA Boards

Student: Anatoly Lerner

Faculty: HSE Tikhonov Moscow Institute of Electronics and Mathematics (MIEM HSE)

Educational Programme: Computer Systems and Networks (Master)

Year of Graduation: 2024

In this paper, we present a subsystem that can be used to effectively distribute global clock lanes between a large number of interconnected FPGAs. The subsystem we propose is FPGA friendly, uses a small number of inter-FPGA connections, and does not require specialized components to operate. A multi-FPGA prototype was built to study the characteristics of the proposed subsystem within the framework of a 4x4 mesh topology. A Russian IT company, YADRO, is interested in research results. This paper contains 43 pages, 20 sources and 21 pictures

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